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Abstract

A semiconductor integrated circuit has a primary delay controller for receiving an external control signal, at least one intermediate delay controller cascaded to the primary delay controller, and a final delay controller cascaded to the intermediate delay controller. The semiconductor integrated circuit further has a phase comparator and a pulse signal generator. The phase comparator compares a phase of the external control signal with a phase of an output signal of the final delay controller, and controls delays in the primary, intermediate, and final delay controllers in accordance with the comparison result. The pulse signal generator receives the external control signal and an output signal of any one of the primary and intermediate delay controllers, and provides a pulse signal whose pulse width is dependent on a period of the external control signal and a value specific to the received output signal. This semiconductor integrated circuit is able to change the pulse width of the pulse signal in response to a change in the frequency of the external clock signal.

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