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Abstract

A method and apparatus for fast decoding of 00H and 0FH mapped instructions. A set of instruction bytes are selected for length decoding. Instruction bytes that contain no length information, such as 0FH opcode bytes in the Intel architecture instruction set, are detected and shifted out of the set before length decoding to determine the length of an instruction is performed on the set. Removing instruction bytes that contribute no length information allows the length decoder logic to be optimized for size and speed. In one embodiment, parallel length decoder sets that each include a detector, shifter, and length decoder operate in parallel on a line of instruction bytes prefetched from an instruction cache. In one embodiment, the length decoders are PLAs (programmable logic arrays) that are combined with separate shifters and detectors logic. This embodiment advantageously allows smaller PLA length decoders. In another embodiment, each set of detector, shifter, and length decoder is implemented in a single PLA. In this embodiment, the detector/shifter/length decoder PLAs are larger but can be optimized for greater overall speed. The present invention is advantageously used to determine the length of multiple variable length instructions before the instructions are decoded for execution.

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First Claim