Data processing with multiple instruction sets
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United States of America Patent
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Apr 14, 1998
Issued Date -
N/A
app pub date -
Oct 22, 1996
filing date -
May 3, 1994
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A data processing system is described utilising two instruction sets. Both instruction sets control processing using full N-bit data pathways within a processor core 2. One instruction set is a 32-bit instruction set and the other is a 16-bit instruction set. Both instruction sets are permanently installed and have associated instruction decoding hardware 30, 36, 38.
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