Method for making planar metal interconnections and metal plugs on semiconductor substrates

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United States of America Patent

PATENT NO 5741741
SERIAL NO

08652175

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for making planar metal interconnections and T-shaped metal plugs for integrated circuits is achieved. The method involves forming a planar insulating (SiO.sub.2) and a hard mask film over a first level of interconnections. A patterned first photoresist layer is then formed for etching trenches in the hard mask film and partially into the planar insulating layer (SiO.sub.2) in which a second level of interconnections are to be formed. The patterned photoresist layer is then laterally etched to expose the hard mask adjacent to the trenches in the SiO.sub.2, and the hard mask is then removed adjacent to the trenches to form a self-aligned mask for the metal plug contact openings. A patterned second photoresist mask aligned over the trenches is then used to etch the contact openings in the trenches, using the hard mask to form T-shaped plug contact openings to the first level of interconnections. The trenches and plug contact openings are concurrently filled with CVD aluminum and chem/mech polished back to form the second level of interconnections with T-shaped metal plugs. The T-shaped metal plugs improve the edge coverage while making it easier to fill the narrow contact openings with aluminum without voids in the metal plugs.

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Patent Owner(s)

Patent OwnerAddress
VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONHSINCHU

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Tseng, Horng-Huei Hsinchu, TW 447 4884

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