Lead on chip package

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5742096
SERIAL NO

07943908

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A lead on chip package comprising a semiconductor chip having a plurality of bonding pads and a plurality of minute protrusions formed at both side portions of the upper surface thereof, an insulating film made of a fluoroethylene film having knurled surfaces, and a plurality of inner leads each directly connected to each corresponding bonding pad of the semiconductor chip and provided with knurled surfaces. The formation of minute protrusions is accomplished by using a radio frequency (RF)-sputtering process at a low temperature. The formation of the knurled surfaces at the inner leads can be accomplished by passing the inner leads between rollers each having a knurled outer surface or by coating a nodule or dendrite layer over the surfaces of inner leads by an electro-plating using a high current density. Using the fluoroethylene film, the insulating film can reduce in thickness. By virtue of the knurled surfaces formed at the inner leads and the insulating film, the adhesion can be improved. It is also possible to prevent an occurrence of parasitic capacitance. As a result, there is provided an effect of assisting packages to be laminate.

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Patent Owner(s)

Patent OwnerAddress
LG SEMICON CO LTDCHEONGJU 1 HYANGJEONG-DONG HUNGDUK-GU CHOONGCHEONGBU-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Hee Gook Gaepo-2nd Woosung Apt. 11-605, Daechi-dong, Kangnam-ku, Seoul, KR 1 4

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