Memory array of integrated circuits capable of replacing faulty cells with a spare
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United States of America Patent
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Apr 21, 1998
Grant Date -
N/A
app pub date -
Apr 27, 1993
filing date -
Nov 2, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fault tolerant random access data storage system comprises a plurality of rows of memory chips 31 plus a first spare row of chips 32 and a second spare row of chips 33, each chip comprising an array of memory locations. A controller 25 addresses the chips with the logical addresses of the rows within the arrays being skewed relative to their physical addresses but in a different manner for the different rows of chips, and with the logical addresses of the columns within the arrays being skewed relative to their physical addresses but in a different manner for the different manner for the different rows of chips. The locations of faults within the chips are recorded so that if a selected array row in a selected chip row 31 is faulty, then a replacement row in the first spare row of chips 32 is selected instead, and if a selected array column in a selected chip row 31 is faulty, then a replacement column in the second spare row of chips 33 is selected instead.
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