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Abstract

Information about the relative phase relationship of the clocks of two chips that are connected with an inter-chip connection is used to adjust the clocks. In the method proposed by the invention, transitions between a good data transfer behaviour to a worse data transfer behaviour are detected as a function of the variable clock delays which delay the chip clock, and a clock delay value between the transitions is chosen. Thus, an optimization of data transmission is achieved, and it can be shown that with this procedure, the clock skew is accurately compensated as well. Additionally, a method for quantifying the variable clock delay, which consists of a multitude of delay elements arranged in a delay chain, is given. In order to do this, the number of delay elements necessary for a delay of half a clock cycle is determined. Thus, a connection between the length of a clock cycle and the delay caused by one delay element is established. With this method of quantifying delays, it is possible to transmit information about the value of the variable clock delay between chips. It is also possible to transmit this information to a central clock adjustment unit, which is especially advantageous in a multi-chip system. The central clock adjustment unit can calculate the appropriate delay values for each chip and thus synchronize a multutude of chips.

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First Claim