US Patent No: 5,745,363

Number of patents in Portfolio can not be more than 2000

Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations

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Abstract

In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.

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First Claim

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Patent Owner(s)

Patent OwnerAddressTotal Patents
LSI LOGIC CORPORATIONMILPITAS, CA4131

International Classification(s)

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  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boyle, Douglas B Palo Alto, CA 35 1743
Jones, Edwin R Sunnyvale, CA 35 2045
Koford, James S San Jose, CA 80 3653
Rostoker, Michael D Boulder Creek, CA 204 9998
Scepanovic, Ranko Saratoga, CA 176 4778

Cited Art

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
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LSI LOGIC CORPORATION (2)
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5,506,788 Similarity-extraction force-oriented floor planner 27 1994
 
HUGHES AIRCRAFT COMPANY (1)
4,688,072 Hierarchical configurable gate array 55 1986
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
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RICA CORPORATION, A CORP. OF DE (1)
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THE UNITED STATES OF AMERICA AS REPRESENTED BY THE SECRETARY OF THE ARMY (1)
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Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
LSI LOGIC CORPORATION (29)
6,085,032 Advanced modular cell placement system with sinusoidal optimization 28 1996
6,026,223 Advanced modular cell placement system with overlap remover with minimal noise 78 1996
5,963,455 Advanced modular cell placement system with functional sieve optimization technique 6 1996
5,914,888 Advanced modular cell placement system with coarse overflow remover 3 1996
5,892,688 Advanced modular cell placement system with iterative one dimensional preplacement optimization 9 1996
5,872,718 Advanced modular cell placement system 4 1996
5,870,311 Advanced modular cell placement system with fast procedure for finding a levelizing cut point 0 1996
6,067,409 Advanced modular cell placement system 108 1997
5,898,597 Integrated circuit floor plan optimization system 100 1997
5,875,118 Integrated circuit cell placement parallelization with minimal number of conflicts 1 1997
5,859,782 Efficient multiprocessing for cell placement of integrated circuits 3 1997
6,186,676 Method and apparatus for determining wire routing 4 1997
6,123,736 Method and apparatus for horizontal congestion removal 86 1997
6,075,933 Method and apparatus for continuous column density optimization 9 1997
6,068,662 Method and apparatus for congestion removal 91 1997
6,070,108 Method and apparatus for congestion driven placement 49 1997
6,058,254 Method and apparatus for vertical congestion removal 85 1997
5,963,975 Single chip integrated circuit distributed shared memory (DSM) and communications nodes 31 1997
6,324,674 Method and apparatus for parallel simultaneous global and detail routing 139 1998
6,289,495 Method and apparatus for local optimization of the global routing 114 1998
6,260,183 Method and apparatus for coarse global routing 33 1998
6,253,363 Net routing using basis element decomposition 107 1998
6,247,167 Method and apparatus for parallel Steiner tree routing 99 1998
6,230,306 Method and apparatus for minimization of process defects while routing 106 1998
6,175,950 Method and apparatus for hierarchical global routing descend 108 1998
6,154,874 Memory-saving method and apparatus for partitioning high fanout nets 60 1998
6,088,519 Method and system for improving a placement of cells using energetic placement with alternating contraction and expansion operations 72 1998
6,182,272 Metal layer assignment 108 1998
6,292,929 Advanced modular cell placement system 84 1999
 
INTEL CORPORATION (7)
6,826,619 Method and apparatus for preventing starvation in a multi-node architecture 4 2000
6,487,643 Method and apparatus for preventing starvation in a multi-node architecture 24 2000
6,772,298 Method and apparatus for invalidating a cache line without data return in a multi-node architecture 8 2000
7,234,029 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture 9 2000
6,791,412 Differential amplifier output stage 2 2000
6,721,918 Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect 8 2000
6,971,098 Method and apparatus for managing transaction requests in a multi-node architecture 22 2001
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
5,956,496 Automated method for circuit optimization 1 1996
6,353,922 Automatic generation of one dimensional data compaction commands for electron beam lithography 4 1999
 
ALTERA CORPORATION (1)
6,301,694 Hierarchical circuit partitioning using sliding windows 9 1997
 
DELL USA, L.P. (1)
6,378,119 Method and system for adaptive component placement 2 1999
 
FREESCALE SEMICONDUCTOR, INC. (1)
6,209,123 Methods of placing transistors in a circuit layout and semiconductor device with automatically placed transistors 293 1996
 
FUNAI ELECTRIC CO., LTD. (1)
6,915,027 Method and an apparatus to speed the video system optimization using genetic algorithms and memory storage 6 2002
 
ILLINOIS INSTITUTE OF TECHNOLOGY (1)
7,243,317 Parameter checking method for on-chip ESD protection circuit physical design layout verification 8 2003
 
KOZA, JOHN R. (1)
6,564,194 Method and apparatus for automatic synthesis controllers 19 1999
 
MENTOR GRAPHICS CORPORATION (1)
8,020,134 Method and apparatus for parallel processing of semiconductor chip designs 0 2008
 
SYNOPSYS, INC. (1)
6,385,760 System and method for concurrent placement of gates and associated wiring 5 1998