Apparatus and method for adjusting the skew of a timing signal using propagation delay time of signals generated by a ring oscillator forming a digital circuit
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United States of America Patent
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Apr 28, 1998
Grant Date -
N/A
app pub date -
May 30, 1995
filing date -
Jun 2, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
When a selector selects a first input terminal, a first loop circuit is formed including first and second input buffer circuits and an output buffer circuit. When the selector selects a second input terminal, a second loop circuit is formed including the first input buffer circuit and the output buffer circuit. When the selector selects a third input terminal, a third loop circuit is formed including the first input buffer circuit, a variable delay line (VDL), and the output buffer circuit. From the oscillating frequencies of loop circuits each formed as a ring oscillator, their respective signal delay times are obtained. By equalizing characteristics of first and second input buffer circuits, through a mutual operation using the signal delay times of respective loop circuits, a propagation delay time over a timing signal supply path including the first input buffer circuit and the VDL and stretching to a flip-flop is obtained precisely.
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