Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching
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United States of America Patent
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May 5, 1998
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Sep 24, 1996
filing date -
Sep 24, 1996
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Abstract
A novel method is presented to form and planarize an inter-metal-dielectric(IMD) layer of an integrated circuit with two or more levels of interconnection metallurgy. The method utilizes chemical-mechanical-polishing(CMP) followed by reactive-ion-etching(RIE) to first planarize and then etch back a deposited IMD layer. Metal line spacings of less than 1.5 microns produce voids in the IMD even when spin-on-glass(SOG) is used to partially fill the spaces prior to IMD deposition. These voids, which contain organic residues and debris, can produce eruptions of material during several subsequent processing steps. The method of this invention attenuates and de-activates these voids, rendering them completely benign. Since CMP is only used to achieve a planar surface, risks of CMP damage to alignment marks and other features are also reduced.
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