OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 5, 1998
Issued Date -
N/A
app pub date -
Nov 14, 1996
filing date -
Jun 17, 1996
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes a plurality of transistor cells arranged in rows and columns. The sources of transistor cells in the same memory block are connected to a main source line through a control gate, as are the drains. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected transistor cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected transistor cells. The associated circuitry for bit-based writing, as well as methods of programming and erasing the memory cell array, with over-program and over-erase repair capability, are also disclosed.
First Claim
Family
International Classification(s)
- No Non-US Classification to display
Cited Art Landscape
Patent Citation Ranking
- No Patent Citation Ranking to display
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully