Method and system for performance monitoring of misaligned memory accesses in a processing system
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United States of America Patent
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May 5, 1998
Grant Date -
N/A
app pub date -
Oct 2, 1995
filing date -
Oct 2, 1995
priority date (Note) -
Expired
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Abstract
A method and system for monitoring performance of a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes identifying misaligned data items, and determining a performance penalty of misaligned data accesses during a predetermined sampling period.
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