Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence
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United States of America Patent
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May 5, 1998
Issued Date -
N/A
app pub date -
Jan 25, 1995
filing date -
Feb 26, 1990
priority date (Note) -
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Abstract
A processor with a branch target cache (BTC) and multiple instruction prefetch storage circuits. A control mechanism allows the fetching of instructions to be transferred from a first prefetch storage circuit to a second prefetch storage circuit which contains branch target instruction bytes. The control is transferred based on a prediction of whether the branch will be taken using history bits associated with the branch instruction. If the processor later determines that the branch is mispredicted, the execution of instructions resumes from the first prefetch storage circuit.
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