Counter having programmable periods and method therefor
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United States of America Patent
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May 5, 1998
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N/A
app pub date -
Jul 2, 1996
filing date -
Jul 2, 1996
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Abstract
A counter (200) generates signals which have an average period of a non-integer multiple of an input clock period. Through the use of this non-integer multiple period, non-integer division operations are executed and used in circuits such as pulse width modulators (800) and phase lock loops (900). Additionally, when the counter (200') is used with a Gray coded counter, the average duty cycle of all bits is exactly equal to 50%.
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