Method and apparatus for reducing warpage of an assembly substrate

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United States of America Patent

PATENT NO 5751556
SERIAL NO

08625794

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Abstract

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A method and apparatus for reducing warpage of an assembly substrate and providing registration between a surface mount technology (SMT) component and the assembly substrate. The SMT component includes mounting pins extending from the component and capable of engaging corresponding apertures in the assembly substrate. Each mounting pin is registrable with a corresponding aperture in the assembly substrate. The mounting pins are capable of providing an interference fit between the SMT component and the assembly substrate.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Butler, Peter O Hillsboro, OR 1 83
Suarez-Gartner, Ricardo E Beaverton, OR 1 83

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