Demultiplexer for a multi-bitline bus
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United States of America Patent
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May 12, 1998
Grant Date -
N/A
app pub date -
Feb 23, 1996
filing date -
Feb 23, 1996
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.
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