Method and apparatus for simultaneously executing instructions in a pipelined microprocessor
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United States of America Patent
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May 12, 1998
Issued Date -
N/A
app pub date -
Sep 3, 1997
filing date -
Feb 8, 1994
priority date (Note) -
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Abstract
An instruction combination unit for a microprocessor compares multiple fetched instructions to determine whether they can be combined for simultaneous execution. The instruction combination unit compares destination registers of preceding instructions against source registers of subsequent instructions. If a subsequent instruction is to operate on a result of a preceding instruction before the result of the preceding instruction is available to the subsequent instruction, a data access conflict arises. The instructions are compared, and combined, if possible. Otherwise, execution of the subsequent instruction is stalled until the result from the preceding instruction is available to the subsequent instruction.
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