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Abstract

A digital signal processor includes a data memory which can be connected to, each of an M-bus, an A-bus, and a B-bus, each serving as a data bus, a pointer for supplying a data address to the data memory, and a decoder for supplying a control signal to the data memory such that one of a read cycle, a write cycle and a read/write cycle is selected in accordance with a result of decoding an instruction. When the read/write cycle has been selected, the data memory outputs data stored at a location designated by the data address from the pointer onto one of the buses, such as the M-bus, while receiving data from another bus, such as the A-bus, and storing the data thus received at the same location as designated by the data address. In one embodiment, the data memory includes a write circuit which has a latch circuit for temporarily holding data received from the data bus in a given memory cycle preceding the read/write cycle. Data is read from a given location in the data memory and another data is subsequently written at the same location in the read/write cycle. For example, two different data buses are used for reading data and writing data, respectively. Consequently, not only the read cycle and write cycle, but also the read/write cycle are enabled, which implements a data memory higher in performance than conventional ones without using a technique of increasing the speed of circuit operation.

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