Power conservation in synchronous SRAM cache memory blocks of a computer system
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United States of America Patent
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May 12, 1998
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N/A
app pub date -
Jul 14, 1995
filing date -
Jul 14, 1995
priority date (Note) -
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Abstract
A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors the CPU bus cycles in order to shut off the clocking signals supplied to the cache SRAM memory blocks when the CPU is not accessing the cache memory, thereby reducing the power consumption of the high-power SRAM devices. The power conservation apparatus resumes standard synchronized clocking to the cache SRAM blocks when the CPU is performing a cache-hit memory access cycle for maximum cache access performance.
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