Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
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United States of America Patent
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May 12, 1998
Grant Date -
N/A
app pub date -
Oct 2, 1995
filing date -
Oct 2, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.
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