System and method for enabling and disabling writeback cache
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United States of America Patent
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May 12, 1998
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N/A
app pub date -
Jul 25, 1996
filing date -
Jul 25, 1996
priority date (Note) -
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Abstract
A cache memory system operates without requiring valid bits in the external cache tag RAM by employing a system controller as a writeback cache controller for control of the cache data/tag memory and the system main memory. The system controller receives signaling information from a CPU through a host bus to indicate when to pre-load the cache memory or to flush (disable) the cache memory while maintaining memory coherencey by causing the cache controller to write back all modified lines in the cache memory to the main memory.
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