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Abstract

A method for performing data transfers in a computer system comprising an improved DMA controller (DMAC) for performing DMA transfers between a peripheral device and system memory and receiving and servicing interrupts generated by the peripheral device. The system comprises a CPU, system memory, the DMA controller and a plurality of peripheral devices interconnected by buses. The CPU programs the peripheral, such as a disk drive, to retrieve or store data. When the peripheral has retrieved the data or is ready to receive the data the peripheral generates an interrupt. The CPU programs the DMAC to perform DMA transfers between the peripheral and the system memory and to selectively decouple the interrupt request from the peripheral to the CPU so that the DMAC can service the interrupt from the peripheral rather than the CPU. The decoupling is selectively performed so that, in the case of a write to the peripheral, the DMAC can receive the interrupt from the peripheral and perform the data transfer. In the case of a read from the peripheral, the DMAC performs the data transfer, then receives and services the interrupt from the peripheral. The CPU also programs the DMAC to selectively generate an interrupt to the CPU upon completion of DMA transfers. The CPU also programs the DMAC to selectively wait for an interrupt from the peripheral before performing the DMA transfers. The CPU also programs the DMAC to selectively poll for status in the peripheral and check for error conditions.

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