High speed packet switch
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United States of America Patent
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May 26, 1998
Grant Date -
N/A
app pub date -
Jan 16, 1996
filing date -
Jan 16, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A high speed packet switch which is inherently non-blocking, requires a minimum amount of buffering, is modular and degrades gracefully with failures. The output destination buffers can each absorb data at the full switch rate to avoid contention and they are filled evenly to minimize buffer size. The architecture only requires few parts types (multiplexers, demultiplexers and crosspoint switches) to operate at high speeds. The output list offers considerable flexibility in the way the data is output, whether it is by priority and/or by time division multiplexed sub destinations.
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