Error detection and correction for four-bit-per-chip memory system
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United States of America Patent
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May 26, 1998
Grant Date -
N/A
app pub date -
Oct 3, 1995
filing date -
Oct 3, 1995
priority date (Note) -
Expired
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Abstract
Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory systems. The code structure enhances utilization of chip real estate and specifically provides for the utilization of a (76,64) code which employs 19 chips per computer memory word as opposed to 20 chips per word.
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