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Abstract

A system to transfer a serial digital data protocol between a controlling processor such as digital signal processor and a plurality of analog front-end devices is described. The system has a serial clock unit to generate a serial clock reference signal, a serial data control unit to create the serial data protocol, a serial clock transmission medium, a serial data transmission medium, and an analog front-end control unit. The serial digital data protocol has a start bit time, an address time, a read/write bit time, a first high impedance time, a serial data word time, a second high impedance time, and a stop bit time. A serial data word may be transferred either from the controlling processor to the analog front-end device or from the analog front-end device to the controlling processor dependent on the state at the read write bit time.

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First Claim