Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction
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United States of America Patent
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May 26, 1998
Issued Date -
N/A
app pub date -
Feb 7, 1997
filing date -
Oct 14, 1994
priority date (Note) -
Expired
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Abstract
Redundant mapping tables for use in processors that rename registers and perform branch prediction is presented. The redundant mapping tables include a plurality of primary RAM cells coupled to a plurality of redundant RAM cells. In the event of a branch instruction, the redundant RAM cells can save the contents of the primary RAM cells in a single clock cycle before the processor decodes and executes subsequent instructions along a predicted branch path. Should the branch instruction be mispredicted, the redundant cells can restore the primary RAM cells in a single clock cycle. A branch stack, coupled to the redundant mapping tables, updates restored mapping tables with changes made for preceding instructions that were decoded in parallel with the branch instruction. A plurality of levels of redundant RAM cells may be used to enable the nesting of a plurality of branch predictions at any one time.
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