Importance

Loading Importance Indicators...

Abstract

A computer system including amongst its components a host bus coupled to a processor, an intermediate (PCI) bus, an expansion (ISA or EISA) bus, a host bridge coupled between the host and intermediate busses, and an expansion bridge coupled between the intermediate and expansion busses, is disclosed. The host bridge incorporates data buffer management circuitry which examines a write request presented to the host bridge to determine whether the write request is to a device not coupled to the expansion bus. If the write request is to a device not coupled to the expansion bridge, the buffer management allows the write buffer to accept write data associated within the write request. If not, the buffer management circuitry prevents the write buffer from accepting the write data associated with the write request. The data buffer management circuitry may be configured to determine specifically whether the write request is to a graphics frame buffer.

Loading the Abstract Image...

First Claim