Semiconductor package having a eutectic bonding layer
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United States of America Patent
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Jun 2, 1998
Grant Date -
N/A
app pub date -
Jun 25, 1996
filing date -
Jun 25, 1996
priority date (Note) -
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Abstract
A package for a backside-ground high power transistor comprises a metal base, a flat insulator layer on the base defining a window for receiving the transistor and a pair of flat metal layer bonded to the upper surface of the insulator layer, the flat metal layers serving as electrical leads for connection to the collector and drain of the transistor received therein. A method for bonding a ceramic to a metal is also provided by the present invention. The method comprises the steps of contacting eutectic-forming layers on a common shim structure with ceramics and metals, heating the eutectic-forming layers to a temperature that is greater than the melting temperature of the eutectic-forming layers, and allowing the eutectic-forming layers to solidify, thereby bonding the ceramic to the metal.
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