Clock skew minimization system and method for integrated circuits
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United States of America Patent
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Jun 2, 1998
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N/A
app pub date -
Aug 20, 1996
filing date -
Aug 20, 1996
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Abstract
A precise and highly controllable clock-distribution network is provided on one active substrate to distribute clock signals with minimal skew to another active substrate by connecting the substrates together face-to-face using flip-chip technology. Since the clock-distribution substrate is sparse, 'quiet busses' are provided on the sparse substrate to facilitate the high-speed transfer of data over relatively long distances. Low-power devices (e.g., DRAM) can be provided on one substrate for use by higher-power logic (e.g., a processor) on another substrate with minimal interconnection distance.
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