Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
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United States of America Patent
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Jun 2, 1998
Grant Date -
N/A
app pub date -
Jan 17, 1996
filing date -
Jan 17, 1996
priority date (Note) -
Expired
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Abstract
A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.
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