DC offset compensation device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5760629
SERIAL NO

08683309

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A level detector 2 detects variation of the amplitude of an input signal a to output a level signal b representing HIGH or LOW in order to define the head portion of the input circuit a. A time constant control signal 3 generates a time constant control signal c based on the level signal b to control a time constant of an estimator 4 so as to make the time constant small for a prescribed period from a time when the level signal b varies from HIGH to LOW. The estimator 4 estimates DC offset included in the input signal a with the a time constant variation according to the time constant control signal c to output an estimate d. A compensator 1 subtracts the estimate d from the input signal a to obtain a compensation output. Therefore, in the estimator 4, the speed of estimating the DC offset is different between a period corresponding to the head portion of the input signal a and other periods. Thus, a DC offset compensation device can be configured to be capable of fast DC offset compensation at the head portion of the input signal a and stable DC offset compensation at the other portions.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
MATSUSHITA ELECTRIC INDUSTRIAL CO LTDOSAKA JAPAN

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takai, Hitoshi Toyono, JP 55 748
Tatsuta, Akihiro Kashiwara, JP 39 661
Urabe, Yoshio Ibaraki, JP 239 1102
Yamasaki, Hidetoshi Amagasaki, JP 26 458

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation