Programmable logic array integrated circuits with enhanced carry routing
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United States of America Patent
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Jun 2, 1998
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app pub date -
Jun 30, 1995
filing date -
Nov 4, 1994
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Abstract
A programmable logic device (10) has a number of programmable logic elements (LEs) (12) which are grouped together in a plurality of logic array blocks (LABs) (14). A global interconnect structure (20, 24) is provided for interconnecting a LAB with other LABs. Adjacent or nearby LABs are directly connectable to one another to provide a direct carry chain (70a, 70b) between LABs. The carry chain is enhanced by providing a selector (80) that allows a LAB's carry input to selectively be coupled to either the carry output of an adjacent or nearly LAB or to the global interconnect.
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