Sub-word line driver circuit for memory blocks of a semiconductor memory device
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United States of America Patent
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-
Jun 2, 1998
Grant Date -
N/A
app pub date -
Dec 16, 1996
filing date -
Dec 16, 1996
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A block selecting scheme for a memory device. The block selecting scheme includes a sub word line driver circuit having multiple sub word line drivers and an inverter circuit. For one embodiment, the sub word line driver circuit includes four sub word line drivers. Each sub word line driver is used to select the sub word line for a corresponding memory block. Each of the sub word line drivers is coupled to a global word line via the inverter circuit. Furthermore, each of the sub word line drivers operates as an inverter. By coupling the global word line and each of the sub word lines via two inversion circuits, the global word line and the sub word lines are typically at the same voltage level. Thus, the deleterious effect of shorting between adjacent global word lines and sub word lines is substantially reduced. Furthermore, by grouping more than two sub word line drivers together, the overall die size of the memory device may be reduced.
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