Signal processing apparatus and method
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United States of America Patent
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Jun 2, 1998
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jun 7, 1995
priority date (Note) -
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Abstract
An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.
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