Virtual interconnections for reconfigurable logic systems
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United States of America Patent
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Jun 2, 1998
Grant Date -
N/A
app pub date -
Sep 28, 1995
filing date -
Apr 1, 1994
priority date (Note) -
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Abstract
A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A 'softwire' compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.
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