Method and apparatus for scan testing with extended test vector storage in a multi-purpose memory system
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United States of America Patent
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Jun 2, 1998
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N/A
app pub date -
Apr 17, 1995
filing date -
Apr 17, 1995
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Abstract
A data processor (12) has built-in circuitry for scan testing certain circuits. The data processor generates and stores test vectors in a memory system (22) normally used for data and instruction storage. These vectors can be much larger than the size of any scan chain. During testing, the stored vectors are automatically routed to the circuits to be tested (36, 38) and the outputs compared to a benchmark. The data processor (12) need not pause to generate additional test vectors. Therefore, the data processor (12) can use a single circuit to generate scan data and compress scan results with minimal timing or size implications.
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