On-chip memory map for processor cache macro
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United States of America Patent
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Jun 2, 1998
Issued Date -
N/A
app pub date -
Jun 6, 1995
filing date -
Jul 31, 1991
priority date (Note) -
Expired
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Abstract
A computer processor architecture which employs an on-chip cache macro and an on-chip memory map is described. The memory map contains indicia of the cachability of different segments of off-chip memory, preferably along with an indication of the read/write status of each off-chip memory segment. A processor generated address signal is then compared on-chip with the memory map to ascertain whether the generated signal falls within a segment which is cachable or uncachable and which is read-only or read/write.
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