Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor
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United States of America Patent
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Jun 2, 1998
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Nov 30, 1993
priority date (Note) -
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Abstract
A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
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