CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers
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United States of America Patent
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Jun 9, 1998
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N/A
app pub date -
Feb 28, 1997
filing date -
Feb 28, 1997
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Abstract
A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.
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