Patterned filled layers for integrated circuit manufacturing
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United States of America Patent
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Jun 9, 1998
Grant Date -
N/A
app pub date -
Jul 1, 1996
filing date -
Jul 1, 1996
priority date (Note) -
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Abstract
A metal layer on an integrated circuit includes active signal lines and fill metal segments. The fill metal segments are polygons. Each fill metal segment at its narrowest has a width which is not greater than 1.25 times a design rule metal pitch for a technology used to fabricate the integrated circuit. In addition, each fill metal segment is separated from every other fill metal segment by spacing which is at least 0.7 times the design rule metal pitch for the technology used to fabricate the integrated circuit. Also, each fill metal segment is separated from every active signal line by spacing which is at least 0.5 times the design rule metal pitch for the technology used to fabricate the integrated circuit.
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