Intelligent binning for electrically repairable semiconductor chips
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United States of America Patent
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Jun 9, 1998
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N/A
app pub date -
Aug 2, 1996
filing date -
Aug 2, 1996
priority date (Note) -
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Abstract
The present invention relates to a system and method for testing one or more semiconductor devices (e.g. packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable. The semiconductor device may be binned differently depending on the number of identified failures. The decision circuitry may designate the semiconductor device for an additional procedure, if the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair, if the number of the identified failures is within a second number set. The decision circuitry designate the semiconductor device for additional tests of the first type, if the number of the identified failures is within a third number set. The tests of a first type may be a hot sort procedure and the additional tests may be a cold final procedure.
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