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Abstract

A superscalar processor has two pipelines that include decode, operand read, execute and writeback stages. An instruction datapath circuit of the processor comprises a plurality of result buses coupled to a corresponding plurality of write ports of a register file. Read ports of the register file are coupled to multiplexer logic which selects operands for various operations specified by instructions. Execution results of the operations are provided on the result buses. Each register of the register file has a status bit that is set responsive to a multiplication operation which specifies data stored in the register. The status bit is reset responsive to generation of a product from the multiplication operation. Processing of a latter instruction in the pipelines is halted when the latter instruction specifies the register and the status bit is set. Also included is a bypass mechanism that allows a result produced during the execute stage to be bypassed to the read stage of a subsequent instruction.

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First Claim