CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain
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United States of America Patent
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Jun 16, 1998
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N/A
app pub date -
Aug 29, 1996
filing date -
May 11, 1990
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Abstract
A process sequence for fabricating CMOS devices of the LDD type includes forming spacers along the sides of gates defined on p- and n-regions of the device. In a two-mask sequence, a thin layer of silicon dioxide is utilized to protect the n-region spacers while the p-region spacers are etched away. In one-mask variants of this sequence, a thin layer of silicon oxynitride is utilized to prevent oxide growth over one type of region while an oxide implant mask is grown on the surface of the other type of region and on exposed surfaces of the gates overlying the other type of region.
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