Method of forming a recessed interconnect structure

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United States of America Patent

PATENT NO 5767012
SERIAL NO

08660674

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Abstract

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A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.

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Patent Owner(s)

Patent OwnerAddress
GLOBALFOUNDRIES INCMAPLES CORPORATE SERVICES LIMITED PO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bandyopadhyay, Basab Austin, TX 56 1434
Brennan, William S Austin, TX 56 1608
Dawson, Robert Austin, TX 146 3861
Fulford, Jr H Jim Austin, TX 187 5367
Hause, Fred N Austin, TX 115 2840
Michael, Mark W Cedar Park, TX 106 2828

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