Importance

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Abstract

The timing signal output from a subject circuit is accurately skewed relative to a base clock signal period. A phase-locked loop ('PLL') and sample delay circuit are implemented with the subject circuit. The PLL receives the base clock signal and generates a local clock signal. The local clock signal is input to a sample delay circuit and the subject circuit. The sample circuit generates a delay approximating that of the subject circuit. The output of the sample delay circuit is fed back into the PLL. With the base clock as the PLL's reference signal and the delayed signal as the feedback signal, the local clock signal phase is forced to precede the base clock phase by the propagation delay of the sample delay circuit. In effect, the propagation delay is nulled out. For a PLL generating multiple output phases a zero phase goes to the sample delay circuit and an output with a phase corresponding to a desired skew goes to the subject circuit. Also, a class of logic devices is defined in which propagation delays are nulled out.

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First Claim