Controlled delay circuit for use in synchronized semiconductor memory
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United States of America Patent
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Jun 16, 1998
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N/A
app pub date -
May 13, 1997
filing date -
May 13, 1996
priority date (Note) -
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Abstract
A controlled delay circuit for use in a synchronized semiconductor memory, comprises a reference delay, a delay circuit for controlling an internal circuit, and a comparing and adjusting circuitry comparing a delay amount of the reference delay with a cycle of an external synchronous signal, at a mode register setting time, for automatically adjusting a delay time of the delay circuit on the basis of the result of the comparison.
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