Importance

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Abstract

A pipeline control system for implementing a virtual architecture having complex instruction set is distributed over RISC-like semi-autonomous functional units in a processor. Decoder logic fetches instructions of the target architecture and translates them into simpler RISC-like operations. These operations, each having an associated tag, are issued to the functional units. Address processing unit computes addresses of the instructions and operands, performs segment relocation, and manages the processor's memory. Operations are executed by the units in a manner that is generally independent of operation processing by the other units. The units report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. Thus, the functional units enable multiple operations to be executed in a speculative and out-of-order manner to fully utilize the resources of the processor.

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First Claim