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Abstract

An internal tri-state bus is provided in a field programmable gate array (FPGA). The FPGA is comprised of an input/output interface which receives input data and generates output data. User-configurable logic cells are included within the FPGA and are coupled to the input/output interface through interconnect elements. The interconnect elements provide a number of conductive elements which supply input signals to the logic cells and receive output signals generated by the logic cells. At least one of the logic cells contains at least one output and multiple logic elements which typically include AND gates, multiplexers and registers. The logic elements receive input signals from the interconnect elements, perform digital functions on the input signals and generate output signals to the interconnect elements. At least one logic cell in the FPGA contains a tri-state buffer which is coupled to at least one output of the logic cell. In response to an enable signal provided to the tri-state buffer, the tri-state buffer selectively provides one of the output signals to the interconnect elements. The enable signal may be any input signal supplied to a logic cell. Additionally, the enable signal may enable a tri-state buffer to provide an output signal to an interconnect element when the enable signal comprises either a high logic level or a low logic level. In an alternative embodiment an enable signal may be generated by a logic element within the logic cell.

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