Structure and method to prevent over erasure of nonvolatile memory transistors
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United States of America Patent
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Jun 30, 1998
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N/A
app pub date -
Dec 23, 1996
filing date -
Dec 26, 1995
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Abstract
A method and structure for preventing over erasure in non-volatile memory cells uses simultaneous erase and program current injections which offset one another. These currents come from two separate injection points within the non-volatile memory transistor and are dominant at different points during the erase operation. The first occurring current erases the non-volatile device and the second prevents over erasure.
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