Importance

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Abstract

A package for a semiconductor chip is provided which incorporates a plurality of levels of interconnect--conductive layers within the package which selectively direct signals to and from pins of the die and/or the pins of the package. A single general purpose chip may thus be fabricated in large quantities with the interconnect of the package used to define the specific purpose, functionality and pinout of the final device. Similarly, a standard package may be built to work with a large class of different chips and only the interconnect layers in the package need to be modified to allow the package to work with each different chip. In a second aspect of the invention, one or more layers of interconnect in the package may contain active electronic components which may be connected to nodes of the chip through the interconnect of the package and through the pins of the die. Accordingly, devices which are difficult or impossible to incorporate into a semiconductor die may be incorporated into a single package along with the die. In a third aspect of the invention, a method of integrated circuit design includes using a conventional CAD design tool software package to design not only the integrated circuit, but also variable circuit elements (such as interconnect and electronic components) embedded in the chip package. In a fourth aspect of the invention, a testing methodology for wafer die subcomponents is provided.

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First Claim